Sequential Circuit
The output depends on what happen before and its inputs
ie it has a memory
Synchronous: Outputs change at specific time
Asynchronous: Output change at any time
Bistable - 2 Stable states
Memory Elements
Using a command, we can issue set, reset, no change and memorise.
The memory element will not change the value until a new command is given
Memory element sometimes take in clock
- Triggered by positive pulses
- Triggered by positive edges
- Triggered by negative edges
Latches
- Triggered by pulse
SR Latch
Takes in 2 inputs, set and reset
Gives out 2 outputs, Q and Q'
(Active High)
Uses a high to activate
Set - > Q = 1
Reset -> Q = 0
Set - > Q = 1
Reset -> Q = 0
This Circuit will break when both input is 1 because it breaks the convention of Q and Q'
We will realised that the Q will remember the previous output if its no change (0,0)
(Active Low)
Uses a low to activate
Its invalid if both bits are 0
(Gated SR)
Just add a enable and 2 AND gate.
Outputs change only when EN is high
Its invalid if both bits are 0
(Gated SR)
Just add a enable and 2 AND gate.
Outputs change only when EN is high
D Latch (Direct Latch)
Only takes in one data input and one enable
Makes use of SR latch.
Ensures that there is only one input
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| Characteristic table - D latch |
D latch are used as a cache/memory
Latches: Shortcoming
- Affect only at the start of a clock cycle
- Maintain the value for the entire clock duration
There are certain times where the Q changes when D change..
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| An example of Gated D Latch with en |
this is not the requirement as our requirement is to only change at the start of the clock
Flip Flop
- Triggered by edge
- Synchronous bistable devices
- Synchronous bistable devices
S-R FF
Takes in 3 inputs, s and r and a clock.
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| Characteristic table - SR FF |
Only changes it state at clock edges.
D FF
Triggers at positive edge
Takes in 2 input, clock and D
Similar to SR FF
Application
- Parallel data transfer
To transfer logic circuit outputs x,y, z to ff Q1, Q2 and Q3 for storage
JK FF
Theres is 2 flip backs in this circuit.
Since there's a nand gate, all inputs have to be 1 so it can activate.
Toggle state when both input is 1.
No change when both is 0
T FF
2 input, 1 input and 1 clock
Uses JK flip flop and only toggles
Asynchronous Inputs
The input can affect the state of the FF independent of the clock.
Flip flops can support Asynchronous Inputs as well.
JK FF with Preset and Clear
Acts the same as jk only have 2 extra inputs: Preset and clear.
Preset and clear allows the ff change regardless of the clock is.
As you preset, the output will always remain one. Same for clear
SUMMARY:
