Data Path
Datapath
- Collection of Components that transform data (Arithmetic/logical/memory)
Control
- Tells datapath,memory, I/O devices and tells them what to do base on instructions
Implementation
Instruction Execution Cycles
- Fetch
Bring the instruction from memory.
We need the PC/ Storage (IR) to hold the address
- Decode
We have a 32 bits 1 and 0s
Decode to find out what the instruction is.
- Operand Fetch
Fetch the operands, take the values from the register
- Execute
Do the operation
- Result write
Store the result back to register or memory.
Clock Signal
Uses a stable clock signal which are square wave
One cycle is define as one up and one down
Every cycle can be define on how long (0.5s)
In one second, how many cycle?
The clock time is measured in seconds
Clock rate = 1/ cycle time (sec) HZ
1 HZ = 1 cycle / second
Mips instruction execution
LoadWord
Fetch
lw $3, 20($1)
Decode
Read $1 as op1
Use 20 as op2
Execute
1. Memadd = OPr1 +opr2
Memory Access
Use memadd to read from memory
Result/Write
Memory data stored in $3
BEQ
beq $1, $2, label
Fetch
lw $3, 20($1)
Decode
Read $1 as op1
Use $2 as op2
Execute
1. Compare if op1 == op2
2. Calculate target
Result/Write
If jump,
PC is target
Building a Mips Processor
Fetch Stage
1. Use PC register to fetch instruction from memory
Pass the address to instruction memory.
2. Increment PC by 4 bytes
Use a adder to add a hard-coded 4
3. Pass added address to decoder
Clocking
The clock signal (Rising edge) is use to determine when the address is calculated and pass.
During rising edge, the address is pass to adder and decoding stage.
The added address will only override the PC during the next clock edge
The clock speed controls how fast instruction is being passed.
Decoding Stage (Op fetch)
1. Gather data from instruction field
2. Input from fetch stage
3. Pass to execution stage
- Uses regWrite control signal to control when to write and read.
(Element) Register file:
A collection of 32 register (like an array)
Read at most 2 reg per instruction
Write at most 1 reg per instruction
Take 5 bits each.
Take 5 bits each.
R Type Instruction
add $8 $9 $10
add $8 $9 $10
$10 -> Read
$9 -> Read
$8->Write
I type instruction
addi $21, $22 , -50
$22 -> read
$21 -> read (Mistake)
-> Write (Use a multiplexer)
Multiplexer
Selects one input from multiple input lines
Using a control pin, control which input is allowed to go through
There is only one output.
R type instruction -> read the 5 bits from RD for WR
I type instruction -> do not read from imm for WR, but from RT
-> the RR2 is redundant except branch instructions
-> the RR2 is redundant except branch instructions
Use sign extend and a multiplexer to add the immediate to the solution.
Sign extend is because immediate is 16 bits and multiplexer is expecting 32 bit.
Sign extend is because immediate is 16 bits and multiplexer is expecting 32 bit.
Execute Stage (ALU stage)
Input: two 32- bit number
Control: 4 bit to decide the particular operation
e.g
if we want to do add, supply 0010
Output:
- Result of operation
- Gives you separate one bit if results is equal to 0
Branching
1. Calculate if the branch is taken (Compare register)
Take one register minus the other and check if its equal to 0 (Equal)
Since ALU returns a bit if result is 0, use that to check if its equal.
2. Calculate where to jump to (Branch target address)
BTA = PC+4 + (Imm *4)
(1)Take the value from the immediate, left shift 2 times (*4)
(2)Using the previous fetch operation, use it to add to (1)
(3) Put in multiplexer (To check if added because we are sharing it with fetch sequence), put in fetch sequence. Iszero pin from ALU is use as a control for this multiplexer
(4) Mux checks if to go to PC+4 or BTA
(4) Mux checks if to go to PC+4 or BTA
Memory access stage
Only the load and store instruction uses this.
Use the memory address calculated by ALU
All other instruction remain idle
ALU: Computation result to be use as memory address
Result write: Result to be stored into memory
ALU -> Memory -> Result store stage
Input:
Memory address and data to be written for SW
Output:
Data read from memory for LW
Control:
Read and write control, only one instruction can be asserted at any point of time.
If I read, I can't write since I follow a byte.
Alu result is pass into address
Store word needs to supply content to be stored
SW $21, -50($22)
$22 is my source register , $21 is target register
Insert the read data 2 into the write data of the data memory.
Non-memory Instruction
Ensure that the result produce is correct.
Since the ALU is routed to address, we will route another path to MUX and use MemtoReg control to ensure that it works for non memory instruction
1. Use the mux to check when it is a non memory instruction
2. The mux is then connect back to WD in the register. This will allow us to write data for the result.
3. Supply the correct control signal for each of these components.
Input:
Memory address and data to be written for SW
Output:
Data read from memory for LW
Control:
Read and write control, only one instruction can be asserted at any point of time.
If I read, I can't write since I follow a byte.
Result write stage
LW $21, -50($22)Alu result is pass into address
Store word needs to supply content to be stored
SW $21, -50($22)
$22 is my source register , $21 is target register
Insert the read data 2 into the write data of the data memory.
Non-memory Instruction
Ensure that the result produce is correct.
Since the ALU is routed to address, we will route another path to MUX and use MemtoReg control to ensure that it works for non memory instruction
1. Use the mux to check when it is a non memory instruction
2. The mux is then connect back to WD in the register. This will allow us to write data for the result.
3. Supply the correct control signal for each of these components.
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